1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device having a semiconductor memory.
2. Description of the Related Art
In a semiconductor memory, for example, in a DRAM, when data is written into a memory cell, if data stored in the memory cell and data input from the exterior are different from each other, it is necessary to invert the data output state held in a sense amplifier.
An example of the waveform at the time of writing bit line data is shown in FIG. 14.
The potential of a word line WL<0> designated by a row address signal (not shown) is set to a high level and data of a memory cell corresponding to the word line is read out and supplied to a bit line BL<0> and amplified by a sense amplifier. If the DRAM is set in a write operation mode, data input from the exterior is written into the sense amplifier by turning on a column selection transistor (not shown) connected between the sense amplifier and a data line. At this time, it is necessary to invert the output state of the sense amplifier and reverse the potential relation between paired bit lines if data read out from the memory cell is different from data input from the exterior. As a result, the write time becomes correspondingly longer.
Therefore, a technique for activating the sense amplifier at the write operation time, transferring data to the bit line before completion of amplification, setting the paired bit lines to potentials corresponding to write data in a state in which the potential levels of the paired bit lines are not changed to the full amplitudes and amplifying the potential difference by use of the sense amplifier is provided. This technique is disclosed in document 1. According to document 1, a column selection signal is input at different timings in the read operation and in the write operation and the input timing in the write operation time is set at earlier timing.
The potential of the word line is set to a high level and data of a memory cell corresponding to the word line appears as infinitesimal potential on the bit line and is started to be amplified by the sense amplifier. When the DRAM is set in the write operation mode, data input from the exterior is written onto the bit line before amplification of the data by the sense amplifier is completed. In this case, time required for inverting the output state of the sense amplifier becomes shorter in comparison with the waveform shown in FIG. 14. As a result, the write time becomes correspondingly shorter.
Document 1: Jpn. Pat. Appln. KOKAI Publication No. 2-226581